Related Issues (20)
- #enhancement: wavedrom bitfield adding `lanes` to csrconfig HOT 2
- Resolve timescale issues
- Move access and hardware from bitfields to reg HOT 2
- Optional timeout on reads and writes
- bugs in c header generation HOT 3
- Access mode 'rolh' can miss a latch HOT 2
- A write-only register with Hardware 'access' option, uses a undeclared *_rdaccess signal HOT 1
- base_address for RTL modules HOT 2
- Queue read not working when FIFO is ready in advance HOT 2
- VHDL target: compare parametric address to constants HOT 1
- Acess mode 'roc' can miss a latch
- Memory interface support
- Interrupt support
- Enumeration types support
- Addressing mode support
- Constants and expressions support
- feature request: support symbolic constants for `base_address`, (do not require it to be a number) HOT 1
- c-headers: struct and bit field layout are implementation defined...
- Verilog build failed when using multistring description #bug
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