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ai-chip

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

async_fifo

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

books

bst-dme

Bounded-Skew DME v1.3

bullshitgenerator

Needs to generate some texts to test if my GUI rendering codes good or not. so I made this.

clocktree_synthesis

codinginterviewchinese2

《剑指Offer》第二版源代码

cores-swerv

SweRV EH1 core

cplusplus

cts-and-converter-scripts

deoldify

A Deep Learning based project for colorizing and restoring old images

e200_opensource

The Ultra-Low Power RISC Core

east1203.github.io

eda_use

EDA工具，DC、ICC使用的脚本

examplescode

SystemVerilog、Verilog、UVM

fifo

Generic FIFO implementation with optional FWFT

hellogithub

:octocat: Find pearls on open-source seashore 分享 GitHub 上有趣、入门级的开源项目

hexo-theme-3-hexo

hexo主题：三段式设计，极简，方便

hexo-theme-amorfati

A responsive simple theme for Hexo.

hexo-theme-ayer

a clean and elegant theme for Hexo. 🐋

hexo-theme-fluid

:ocean: 一款 Material Design 风格的 Hexo 主题 / An elegant Material-Design theme for Hexo

hexo-theme-snippet

Snippet 简洁而不简单，也许是一款你寻找已久的hexo主题

hexo-theme-yun

☁️ A fast & light & lovely theme for Hexo. 一个对可爱自以为是的 Hexo 主题。

hw

RTL, Cmodel, and testbench for NVDLA

kindle_books

markdownphoto

nlp-beginner

NLP上手教程

nndl.github.io

《神经网络与深度学习》 Neural Network and Deep Learning

nyuziprocessor

GPGPU microprocessor architecture

riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug