AXI-4 Lite transfer fail (Master write) about axi-crossbar HOT 9 CLOSED

Hi Vincent,

in the last commit you mentioned, I also remove the necessary synchronisation between write address channel and write data channel, which is most likely the issue. Now the write data channel uses a FIFO to store the granted access and drive its payload.

Yesterday night I added new test bench configuration to stress some AXI4 configuration as AXI4-lite scenarios and it went well. Probably the testbench doesn't reproduce the issue.

Could you provide me a waveform, your test bench, the test case or any info to help me understand the problem? I'll have time the next days to debug and fix the problem if necessary.

Damien

from axi-crossbar.

By the way which simulator do you use? I currently run my verification environment only with Icarus Verilog 11.

from axi-crossbar.

I may have found the root cause @vincentliu84. Can I ask you to test with this commit please? :)

from axi-crossbar.

Sorry for late response during weekend
I use VCS and Xcelium, also AXI VIPs in my environment, so can you open the fsdb format?
I read the code about mst_switch, and submodule: wch_gnt_fifo
The wch_empty signal is generated by wch_gnt_fifo, and it's judged by wr and rd pointer
but when push signal is from 0 -> 1, the empty signal is still 0
you can check the simple waveform in: https://github.com/vincentliu84/hello-world

from axi-crossbar.

Hi Vincent,

srst is tied to 1 in the waveform, so the circuit remains under reset. You need to choose aresetn or srst and don't drive both.

• aresetn: a asynchronous active low reset, so needs to be driven low to reset then released to 1
• srst: a synchronous active high reset, so needs to be driven high to reset then released to 0

You need to choose for all interfaces the same reset strategy, using aresetn or srst, and be sure all interfaces have been reseted then released to expect a proper core behaviour.

Should be ok with this fix :) By the way the last commits introduced USER support. The test bench has been upgraded to support them and I didn't find (yet) bugs during their usage.

Have a good day
Damien

from axi-crossbar.

This is solved, thanks
but I found another issue , if master 0 is write to slave 1 (1 master , 2 slaves in this scenario)
I see wch signals is routed to channel 1, but wvalid and wready is not
you can check waveform2 in https://github.com/vincentliu84/hello-world
(waveform marked with pink is slave 0, and green is slave 1)
Thanks

from axi-crossbar.

from axi-crossbar.

Should be OK now with commit mentioned above. My test suite ran successfully.

I though it could be handy to create a top level of the core to expose only AXI4-lite interface signals and another for AXI4 (which could be the current one). What do you think ?

from axi-crossbar.

it's solved, thank you so much.
I think it's good idea to seperate the two interfaces

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