dingjinghao Goto Github PK

bstsource1.2

Bounded Skew Clock Tree Routing.

buffer_insertion

clock-network-designer

一种可自动综合且可多扇出配置的均衡型时钟树的设计优化方法

clocktreerouting

Project for CENG4120

clocktreerouting-1

cts

eda-ai

Implementation of NeurIPS 2021 paper "On Joint Learning for Solving Placement and Routing in Chip Design" & NeurIPS 2022 paper "The Policy-gradient Placement and Generative Routing Neural Networks for Chip Design".

elmore-delay-model

Elmore Delay Algorithm for Modeling Timing Delays

git-it

:computer: :mortar_board: Learn Git and GitHub. Try the new desktop version →

htree_clock_synthesis

hw5_simplebufferinsertion

lefdef_util

A LEF/DEF Utility.

openphysyn

EDA physical synthesis optimization kit

paper_reproduction

reproduction paper research in low voltage clock tree design

proj-2018-05-20

Tree optimization

rsyn-x

Rsyn – An Extensible Physical Synthesis Framework

symcts-rs

symmetric-clock-tree

Based on the research enclosed in the project, entitled: Fast Timing Model Independent Buffered Clock-Tree Synthesis.

test_git

threed_dme

M3D CTS based on MIVs&3D ICs.

timing_archs

Python scripts in conjunction with NGSPICE control command to generate timing liberty files.

tob-rsmt

tritoncts

Source codes and calibration scripts for clock tree synthesis

van-ginneken

van-ginneken-buffer-insertion

C code for van ginneken buffer insertion algorithm.

vis

餐饮类消费数据的可视分析系统

wire-sizing-calculations

Wire sizing calculations for spec 55 wire