Comments (7)
mattfel1
commented on August 24, 2024
Looks like there was a little sv lurking in one of the templates. I think I fixed it?
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David-Durst
commented on August 24, 2024
Did you push more fixes? The ones from before lunch didn't work.
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mattfel1
commented on August 24, 2024
The fixes should be on 12918ee. Are there different errors now?
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David-Durst
commented on August 24, 2024
Issue with map 50.
INFO: Helper process launched with PID 6168
ERROR: [Synth 8-2576] procedural assignment to a non-register out is not permitted [/home/durst/build.2019.10.24-01.22.04/map_50.v:66]
INFO: [Synth 8-2350] module RetimeShiftRegister ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:29]
INFO: [Synth 8-2350] module FF ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:70]
INFO: [Synth 8-2350] module SRFF ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:129]
INFO: [Synth 8-2350] module SingleCounter ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:194]
INFO: [Synth 8-2350] module RetimeWrapper ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:256]
INFO: [Synth 8-2350] module RootController_sm ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:284]
INFO: [Synth 8-2350] module SingleCounter_1 ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:494]
INFO: [Synth 8-2350] module x30_ctrchain ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:528]
INFO: [Synth 8-2350] module x47_inr_Foreach_SAMPLER_BOX_sm ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:594]
INFO: [Synth 8-2350] module RetimeWrapper_12 ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:793]
INFO: [Synth 8-2350] module SimBlackBoxesfix2fixBox_1 ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:820]
INFO: [Synth 8-2350] module __1 ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:828]
INFO: [Synth 8-2350] module fix2fixBox ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:841]
INFO: [Synth 8-2350] module x40_sum ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:847]
INFO: [Synth 8-2350] module x47_inr_Foreach_SAMPLER_BOX_kernelx47_inr_Foreach_SAMPLER_BOX_concrete1 ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:880]
INFO: [Synth 8-2350] module RootController_kernelRootController_concrete1 ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:988]
INFO: [Synth 8-2350] module AccelUnit ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:1132]
INFO: [Synth 8-2350] module SpatialIP ignored due to previous errors [/home/durst/build.2019.10.24-01.22.04/map_50.v:1550]
Failed to read verilog '/home/durst/build.2019.10.24-01.22.04/map_50.v'
INFO: [Common 17-83] Releasing license: Synthesis
20 Infos, 0 Warnings, 0 Critical Warnings and 2 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Thu Oct 24 01:22:24 2019...
build.2019.10.24-01.22.04/vivado.log (END)
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mattfel1
commented on August 24, 2024
seems to work now when I ran the script
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David-Durst
commented on August 24, 2024
The pnr completes now but has infinite slack. Are there registers on the start and end of the design?
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David-Durst
commented on August 24, 2024
I do not think there are registers at the end of the circuit:
Since there is a path directly from the logic to the end of the circuit, timing won't run. Could you add registers at the end of the circuit?
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