The OpenFrame Project provides an empty harness chip that differs significantly from the Caravel and Caravan designs. Unlike Caravel and Caravan, which include integrated SoCs and additional features, OpenFrame offers only the essential padframe, providing users with a clean slate for their custom designs.

1. Minimalist Design:

   • No integrated SoC or additional circuitry.
   • Only includes the padframe, a power-on-reset circuit, and a digital ROM containing the 32-bit project ID.

2. Padframe Compatibility:

   • The padframe design and pin placements match those of the Caravel and Caravan chips, ensuring compatibility and ease of transition between designs.
   • Pin types are identical, with power and ground pins positioned similarly and the same power domains available.

3. Flexibility:

   • Provides full access to all GPIO controls.
   • Maximizes the user project area, allowing for greater customization and integration of alternative SoCs or user-specific projects at the same hierarchy level.

4. Simplified I/O:

   • Pins that previously connected to CPU functions (e.g., flash controller interface, SPI interface, UART) are now repurposed as general-purpose I/O, offering flexibility for various applications.

The OpenFrame harness is ideal for those looking to implement custom SoCs or integrate user projects without the constraints of an existing SoC.

1. 44 configurable GPIOs.
2. User area of approximately 15mm².
3. Supports digital, analog, or mixed-signal designs.

This example implements a simple timer and connects it to the GPIOs.

First, clone the repository:

git clone https://github.com/efabless/openframe_timer_example.git
cd openframe_timer_example

Then, download all dependencies:

make setup

In this example, we will harden the timer. You will need to harden your own design similarly.

make user_proj_timer

Once you have hardened your design, integrate it into the OpenFrame wrapper:

make openframe_project_wrapper

1. Connecting to Power:

   • Ensure your design is connected to power using the power pins on the wrapper.
   • Use the vccd1_connection and vssd1_connection macros, which contain the necessary vias and nets for power connections.

2. Flattening the Design:

   • If you plan to flatten your design within the openframe_project_wrapper, do not buffer the analog pins using standard cells.

3. Running Custom Steps:

   • Execute the custom step in OpenLane that copies the power pins from the template DEF. If this step is skipped, the precheck will fail, and your design will not be powered.