cruxml Goto Github PK
Name: CruxML
Type: Organization
Bio: CruxML Pty Ltd
Location: Australia
Blog: cruxml.com.au
CruxML's Projects
bazel_rules_hdl
Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (https://bazel.build)
corsair
Control and Status Register map generator for HDL projects
datasets
🤗 The largest hub of ready-to-use datasets for ML models with fast, easy-to-use and efficient data manipulation tools
fapolicyd
File Access Policy Daemon
minimalcrosscompile
This repo is to investigate how to cross compile python libs with bazel.
rules_verilator
Bazel build rules for Verilator
rules_verilog
Utilities for working with Verilog within Bazel.
rules_vivado
Bazel rules for Xilinx Vivado
rules_xilinx
Bazel rules to interface to xilinx tools such as vivado, vitis_hls and xsim.
verilog-axi
Verilog AXI components for FPGA implementation
vitis-quantizer
A pip installable package to do the vitis model quantization. It is a port/migration of https://github.com/Xilinx/Vitis-AI/tree/master/tools/Vitis-AI-Quantizer/vai_q_tensorflow2.x/tensorflow_model_optimization/python/core/quantization/keras/vitis
zcu216-pynq
Board repo for the ZCU216 RFSOC
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