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anspy

Testing various methods for choosing tANS entropy coding automata

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

axi_riscv_atomics

AXI Adapter(s) for RISC-V Atomic Operations

common_cells

Common SystemVerilog components

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

hd-bitfunnel-gpu

hdlib

hwpe-mac-engine

An example Hardware Processing Engine

hwpe-stream

IPs for data-plane integration of Hardware Processing Engines (HWPEs) within a PULP system

labelme

Image Polygonal Annotation with Python (polygon, rectangle, circle, line, point and image-level flag annotation).

misc-linters

Some Internal Linter Scripts

old-snitch

Lean but mean RISC-V system!

pyflexfloat

A Python wrapper around OPRECOMP's FlexFloat library.

riscv-isa-sim

Spike, a RISC-V ISA Simulator