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Covered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.

License: GNU General Public License v2.0

Makefile 5.53% M4 0.29% Shell 0.92% Perl 3.31% Perl 6 1.08% C++ 1.76% Verilog 10.99% C 58.91% Coq 0.01% Tcl 7.65% Yacc 8.27% Lex 1.27%

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covered's Issues

Covered - Is it an official branch now?

Hi @udara28. Is it an official branch of covered now (aka "is it something confirmed by previous maintainer")? Just want to get more info about your plans regarding this tool, want to try it in my pet projects

View mode

Hello everyone, I am with this issue when I try to run the covered report in the view mode:

$ covered report -view

Covered covered-0.7.10 -- Verilog Code Coverage Utility
Written by Trevor Williams ([email protected])
Freely distributable under the GPL license

ERROR! The -view option is not available with this build

I compiled the source with all of the options before the make:

./configure
./configure --enable-profiling
./configure --enable-debug
./configure --with-mpatrol

Can anyone help me??.

Kind regards,

Checking for race conditions... free(): invalid pointer Aborted (core dumped)

Hi,
I am trying to run covered with:
covered score -t tb_state_machine -v state_machine_tb.v -vcd my_state_machine_dumpfile.vcd -o my_state_machine_covered.cdd

Result:

Checking for race conditions...
free(): invalid pointer
Aborted (core dumped)

Can someone please tell me what the issue here is and how to solve this? Because next, when I am trying to generate report; error arises as:

ERROR! Attempting to generate report on non-scored design. Not supported.

Thanks in advance.

CDD merge error

Hi,

I'm using multiple testbenches to verify the same design (to the top module) via Icarus Verilog.
In the testbench everything is the same, except the task name and its content.
For example,

module tb
<some_pin_declaration>
top dut(
<pin_assign>
);
task a
<somethig_to_do>
endtask
initial begin
a
end
endmodule

task a here might be b in other testbench.

From covered score, I was able to produce corresponding .cdd files.
Yet I got core dumped when I tried covered merge

covered: expr.c:1829: expression_merge: Assertion 'base->line == other->line' failed.

the cdd files seem good separately cuz they can run smoothly to produce report by their own.
Any idea what might cause this error? Thx!

Memory in VCD file

Hi, everyone.
When I try to add memory in the dumpvar command, the VCD file does not output the waveform of the memory.
How do you get the memory value change through the VCD file?

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