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bingoshu's Projects

accdnn icon accdnn

A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

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Altium Desinger

ahb2 icon ahb2

AMBA AHB 2.0 VIP in SystemVerilog UVM

antikernel-ipcores icon antikernel-ipcores

FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations

arm9-compatible-soft-cpu-core icon arm9-compatible-soft-cpu-core

This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

cache-controller icon cache-controller

Cache controller based on verilog with cache coherence for two processors

cophee icon cophee

CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.

cryptech icon cryptech

Collection of CrypTech repos to making cloning easier.

dilithium icon dilithium

High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.

ecc-x64 icon ecc-x64

Elliptic Curve Cryptography in assembly for linux x64

h264 icon h264

H264视频解码verilog实现

huffmancode icon huffmancode

hardware implement of huffman coding(written in verilog)

lisnoc icon lisnoc

LIS Network-on-Chip Implementation

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