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1st-claas

Framework for developing and deploying FPGA logic in the cloud as a microservice for web and cloud applications

1st-claas-warpv

csd_siamese_nets

Incorporating Siamese Networks to accurately perform facial recognition using a limited dataset.

openlane_workshop_vsd

This repository will reflect the work done in the Advanced Physical Design Flow workshop, offered by the folks at VSD. It's a 5 day workshop that aims to educate us on the intricacies of Open Source EDA tools and PDKs as used by industry leaders. Furthermore, it uses Openlane flow to help understand the flow of work when it comes to VLSI designs, starting from the RTL level to the GSDII stage, performing the synthesis, placement, floorplanning, routing and sta required to do so.

raincheck

A smart navigation system that incorporates cutting edge weather prediction to make modern day navigation techniques more efficient for intra-city travel

risc-v-cpu

This is the design of a RISC-V based CPU Micro-Architecture using TL-Verilog

standard_cell_library_characterization

This project aims to characterize the power and timing characteristics of custom designed standard cells using the sky130A process design kit.

time-slots-g-maps-api-s-

This aims to generate 2 cutsomer appropriate time slots for the pickup and dropoff of excess luggage for flight travel from origin to destination respectively. The idea is to make the time slots as per the convenience of the customer and at the same time make it feasible for the commpany to perform its pickup and dropoff.