[XRT] ERROR: failed to load xclbin: Invalid argument / xocl_read_axlf_helper: interface uuids do not match about aws-fpga HOT 4 CLOSED

Hi!

Thanks for your question, I'm glad you were able to solve the issue. Customers are required to use the create_vitis_afi.sh to create AFI's and store artifacts in S3. When loading Vitis images, the scripts call fpga-load-local-image <AFI-ID>. To preserve security and health of the FPGA, all AFI's (verified Xilinx bitstreams and .xclbin files) are loaded by AWS after downloading them from S3. All of the aws-fpga workflows utilize S3 to store artifacts and load images to the FPGA.

If you have any more questions, please don't hesitate to ask!

Thanks,
-Joe

from aws-fpga.

Hi, F1 instances only support .awsxclbin because the customer design needs to be interfaced with the AWS Shell. This process is not done by generic vitis flow which generates .xclbin. Perhaps you may be referring to Xilinx docs and vitis flow for on-prem devices, but for F1 customers are expected to use .awsxclbin for loading their designs into F1 FPGA.

Please reach out to us if you have any questions.

Thanks!
Chakra

from aws-fpga.

uhm, so I guess it's because I haven't been doing create_vitis_afi.sh, i.e. have AWS package it and have it stored in S3. doing that I seem to be able to program the FPGA just fine.
so I'm wondering - is there no way to do this without pushing to s3 every time? I mean it feels like an unnecessary round-trip - and some of the docs I see around (from various repos/sources) would suggest it's not needed (i.e. loading an .xclbin file, not necessarily an .awsxclbin one)

from aws-fpga.

@AWSjoeluc was it the case at some point in the past direct loading of the bitstream was possible - and that's why I was seeing docs mentioning .xclbin (I believe it was some of the reinvent workshop docs from a few years back, but I can't remember exactly which docs I was seeing)? or maybe I'm confusing it with just generic vendor-specific (Xilinx) docs?

just trying to piece together what I've been seeing, not that I remember it that well anymore

from aws-fpga.