Avishka Abeywickrama's Projects
Analysis of zoom meeting data using C language
Config files for my GitHub profile.
Coursera-test
The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 instructions. The designed pipeline CPU was implemented using behavioral modeling in verilogHDL and icarus Verilog was used compile and simulate. gtkWave
Addressing data quality concerns is crucial since it plays a significant role in process mining. Nevertheless, the current strategy frequently targets symptoms rather than underlying issues. So, here presents prevention and mitigation of the data quality issues in event logs.
Handwritten Essay Marking Software is a powerful Tool to grade studentsβ handwritten essays by providing more consistent and objective grading. Automates manual grading by using Optical Character Recognition (OCR), Natural Language Processing (NLP), Machine Learning Model.
Bluetooth chat App using Android Studio - by : @sheiiz @avishka4444 @NirashaSewwandi
CO227 : Department Course Page (Postgraduate) - Group 10
Building a basic RV32IM pipeline
An (unofficial) interim transcript template for undergraduates of eng.pdn.ac.lk (Faculty of Engineering, University of Peradeniya)
Git & GitHub Introduction Series
Student and staff profile website of the Department of Computer Engineering, University of Peradeniya https://people.ce.pdn.ac.lk/
Real time digital clock using C language
some test repo