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apll_01v8_sky130

This repository consists of ngspice simulation files and related files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—40MHZ to 100MHZ at 1.8v)IP worked on in the VSD Online Internship - Batch 3 in collaboration with Sky130 Open PDK by Google.

ashmagicpll

awesome-opensource-hardware

List of awesome open source hardware tools, generators, and reusable designs

bootstrap

bootstrap css file to enhance my html webpage

cores

Various HDL (Verilog) IP Cores

htmlandcss

INTERNSHALA ONLINE TRAINING

oh

Verilog library for ASIC and FPGA designers

opensource_physical_design

This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK

pdkfiles

python_floating_conversions

this repository is for converting real numbers into floating point and vice versa in python

radix-5-fft

VERILOG IMPLEMENTATION OF RADIX-5 FFT

real_time_clock

Verilog Implementation of Real-time-clock

shell_scripting

this repository contains some basic examples of Shell_Scripting

systemverilog-assertion

tcl-scripting

Examples of the TCL Scripts for different purposes and for VLSI Physical Design are provided here for your reference

tcl-tk_scripting

This repository contains TCL/Tk scripting.

tensorflow-examples

TensorFlow Tutorial and Examples for Beginners (support TF v1 & v2)

tl_verilog-basics

traffic_light_controller

Verilog Implementation of Traffic-light-controller

uart

Verilog Implementation of UART

verilog_euclidean_distance_based_sorting

verilog implementation of euclidean based distance sorting

verilogbasiccodes

basic combinational and sequential verilog codes