arch-simulator-sig Goto Github PK
Name: 高阶体系结构研究小组
Type: Organization
Bio: develop high performance risc-v simulator
Location: China
高阶体系结构研究小组's Projects
a53_core
advanced-computer-architecture
体系结构研讨 + ysyx高阶大纲 (WIP
aemu
akita
A flexible, high-performance, user-friendly computer architecture simulator engine
am-kernels
AbstractMachine kernels
asimcore
Asim core library
awb
Architect's workbench
basic_verilog
Must-have verilog systemverilog modules
bsv_tutorial_cn
一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
bullseye
Experimental Toolkit for NSCSCC & ISA & Cycle & Perf Model and Core Emulation
cemu
A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education and research.
chisel-env
Basic chisel difftest environment for RTL design (WIP
code_utils
computer-architecture-and-systems-resources
A curated list of Computer Architecture and Systems resources
computer-architecture-learning
cpu_gs132
Verilog code of Loongson's GS132 core
cpu_gs232
cs6290
CS6290 Advanced Computer Architecture Coursework Projects
difftest
Co-simulation framework for Xiangshan
dramsim3
DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator
dramsys
DRAMSys4.0 a SystemC TLM-2.0 based DRAM simulator.
dreamcorev2
e203-simulator-scarab
esesc
ESESC: A Fast Multicore Simulator
feeder
Instruction feeder interface for Asim CPU models
gem5-with-chinese-comment
Gem5 with chinese comment and introduction (master) and some other std gem5 version.
greenrio-v1.0
Open source RISC-V CPU
greenrio-v2.0
Open source RISC-V CPU
micro-arch-learning
micro-arch-training
How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design
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