Comments (2)
zardus
commented on August 28, 2024
The important changes are commenting out the JITing code, because that makes a lot of assumptions regarding the host and guest architecture being the same, which pyvex violates. You can see those by searching for COMMENTED OUT FOR PYVEX in https://github.com/angr/vex/blob/master/priv/main_main.c.
It's almost certain that some others have piled up as well. We haven't had time to do such maintenance tasks recently due to the CGC, but at some point soon, we're hoping to go through and document our VEX changes better, upstream fixes, and hopefully find (or recruit?) some manpower to get some VEX changes done so that we don't have to maintain a separate fork.
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zardus
commented on August 28, 2024
Feel free to reopen this if you have more questions!
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Related Issues (20)
- Possibly incorrect lifting of add instructions on ArchAMD64 HOT 7
- pyvex for ARM inst. "TBB" and "TBH" HOT 2
- Default values for cc registers? HOT 5
- Is ppc / ppc64 / ppc64le supported? HOT 3
- #include <ffi.h> No Such File or Directory Even after installing libffi-dev HOT 7
- test_spotter.py depends on angr HOT 3
- Register names conflict in MIPS arch (bug) HOT 2
- How to model program termination HOT 9
- Is cortex-m supported? HOT 4
- Error when adding lifters and no max_bytes HOT 2
- Refactor build system to use cffi's setuptools extension HOT 3
- ModuleNotFoundError: No module named 'pyvex.vex_ffi' HOT 3
- Lifter fails on basic blocks containing rdsspq instruction HOT 6
- fnop instruction not lifted
- bnd jumps not lifted
- No such file or directory: '/usr/ports/security/py-pyvex/work-py39/pyvex-9.2.39/pyvex_c/libpyvex.so' HOT 3
- Limit of the number of instructions that pyvex.lift can lift each time HOT 6
- Need guidance for making some RISCV ISA fixes HOT 1
- Can't install on mips64 system HOT 3
- Lifter.lift and _lift are backwards
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