andy-wang1988 Goto Github PK

andy-wang1988

Config files for my GitHub profile.

automatminer

An automatic engine for predicting materials properties.

campusshame

互联网仍有记忆！那些曾经在校招过程中毁过口头offer、意向书、三方的公司！纵然人微言轻，也想尽绵薄之力！

dsp_spartan6-dsp48a1

This is a mini projet, a design for the DSP block Spartan6-DSP48A1 using Verilog. I divided the design into 3 different stages written in three modules and connected them in the top module. A simple testbench is provided in the Top_module.v file.

github-slideshow

A robot powered training repository :robot:

hw

RTL, Cmodel, and testbench for NVDLA

image_signal_processor_isp

mux-verilog

Designing MUX 4:1 using verilog HDL

nfu40341120_wujianchen

nvme_controller

NVMe, Software and hardware

opentitan

OpenTitan: Open source silicon root of trust

pci-e

pipelined-cordic-processor---systemverilog

Cordic

practical-uvm-step-by-step

This is the main repository for all the examples for the book Practical UVM

python

risc-v-fudian

Open source high performance IEEE-754 floating unit

systemrdl-compiler

SystemRDL 2.0 language compiler front-end

uvm_axi

uvm AXI BFM(bus functional model)

wujian100_open

IC design and development should be faster，simpler and more reliable

xiangshan-doc

Documentation for XiangShan

xiangshan_nanhu

Open-source high-performance RISC-V processor

xuantie-c910-fpga

risc-v_open_HP_CPU

yasa

:snail:Yet Another Simulation Architecture