andy-wang1988's Projects
Config files for my GitHub profile.
An automatic engine for predicting materials properties.
互联网仍有记忆!那些曾经在校招过程中毁过口头offer、意向书、三方的公司!纵然人微言轻,也想尽绵薄之力!
This is a mini projet, a design for the DSP block Spartan6-DSP48A1 using Verilog. I divided the design into 3 different stages written in three modules and connected them in the top module. A simple testbench is provided in the Top_module.v file.
A robot powered training repository :robot:
RTL, Cmodel, and testbench for NVDLA
Designing MUX 4:1 using verilog HDL
NVMe, Software and hardware
OpenTitan: Open source silicon root of trust
Cordic
This is the main repository for all the examples for the book Practical UVM
Open source high performance IEEE-754 floating unit
SystemRDL 2.0 language compiler front-end
uvm AXI BFM(bus functional model)
IC design and development should be faster,simpler and more reliable
Documentation for XiangShan
Open-source high-performance RISC-V processor
risc-v_open_HP_CPU
:snail:Yet Another Simulation Architecture