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accelerating-cnn-with-fpga

This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

backpropagation_nn_fpga_implementation

This is the final project for the BP NN FPGA implementation

bankcard-recognizer

Extracting numbers from bankcard, based on Deep Learning. 基于深度学习的银行卡号识别与定位系统。

bitonic_sorter

Bitonic sorter (Batcher's sorting network) written in Verilog.

caravel

Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.

card-crnn-ctpn

CTPN+CRNN bank card number identification(data/test pictures accuary ≈90%)

cnnhwpe

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

e203_hbirdv2

The Ultra-Low Power RISC-V Core

e203plus

upgrade to e203 (a risc-v core)

e902soc

a course design work implemented with xuantie opene902

fifo-shift-register-parametrised

fpga-median

FPGA-based Median Filter

gpio_agent

General Purpose I/O agent written in UVM

kws-soc

This is an SoC design dedicated to Keyword Spotting (KWS) based on a neural-network accelerator and the wujian100 platform.

nuclei-board-labs

Nuclei Board Labs

openc906

OpenXuantie - OpenC906 Core

openc910

OpenXuantie - OpenC910 Core

opene902

OpenXuantie - OpenE902 Core

opene906

OpenXuantie - OpenE906 Core

raven-picorv32

Silicon-validated SoC implementation of the PicoSoc/PicoRV32

riscv-crypto

RISC-V cryptography extensions standardisation work.

riscv-dv

Random instruction generator for RISC-V processor verification

tang_e203_mini

LicheeTang 蜂鸟E203 Core

uart

ARM中通过APB总线连接的UART模块

ucas-covid19

ucas疫情防控每日填报助手

verilogrisc

基于蜂鸟E203的魔改

wujian100_open

IC design and development should be faster，simpler and more reliable