Problem with sythesizing - VCU108 - fpga_1g about verilog-ethernet HOT 3 CLOSED

Usually when I see that error, something is either screwed up with clocking somewhere and/or a large portion of the design was optimized away. Did you modify the verilog at all, or did you import all of the files as-is? Also, you may need to run the IP TCL files via the TCL console or something in vivado in order to create the IP cores.

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Thank you for the reply. I found the issue. My constraints file were not in the correct order, hence the error. I corrected it and the design simulated fine. But still it doesn't work in the hardware. The IP is reachable when I check it. But for some reason I cannot loopback.

I am trying the loopback in a Linux machine. Regarding the IP cores I see only one TCL file that generates the PCS/PMA core. Are there other TCL files too..??

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hi it looks all this time i was not matching the gateway ip with my host PC ip.. It works fine now..

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