Name: Alenkruth
Type: User
Company: University of Virginia
Bio: Computer Engineering PhD student at The University of Virginia. I work on Computer Architecture, Hardware Security, and RTL design and verification.
Twitter: alenkruth
Location: Charlottesville, VA.
Blog: alenkruth.com
Alenkruth's Projects
AES core capable of performing AES 256 Encryption in CTR/GCM modes.
My Personal Website.
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
Solutions to the Assignments
A parameterizable CRC accelerator written in System Verilog.
RI5CY from the PULP Platform modified to support Crypto instructions [Work in Progress]
Software workload management tool for RISC-V based SoC research. This is the default workload management tool for Chipyard and FireSim.
Gem5 to McPAT parser with multicore and cache support
SonicBOOM: The Berkeley Out-of-Order Machine
Spike, a RISC-V ISA Simulator
Rocket Chip Generator
Value predictor built for the CS6354 course