Comments (5)
trcwm
commented on July 21, 2024
3
My Terasic DE0 now gets the '\' WozMon prompt!
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trcwm
commented on July 21, 2024
I now also see this exact behaviour in the IVerilog simulation! (I have removed the signal forcing, as this was a dirty hack).
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trcwm
commented on July 21, 2024
As suspected, the CPU enters the BRK state. I'm unsure why still..
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trcwm
commented on July 21, 2024
assign IR = (IRQ & ~I) | NMI_edge ? 8'h00 : IRHOLD_valid ? IRHOLD : DIMUX;
The instruction register gets (unexpectedly) loaded with 0x00 instead of 0xA0 because I changes to 0 (interrupt condition?) for some reason. This triggers the RESET / BRK condition.
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trcwm
commented on July 21, 2024
Found the problem: irq_n and nmi_n are active low, but IRQ and NMI to the 6502 core are active high!
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Related Issues (20)
- Fix to Makefile for board olimex_ice40hx8k_evb_ice40-io HOT 2
- build process does not work HOT 2
- The link to the Olimex board in the README.md now goes to the wrong board HOT 1
- Modify to load as a MiSTer core? HOT 8
- Issue with PS/2 keyboard on Terasic DE0 Board HOT 22
- Can't change colors on Olimex iCE40HX8K with ICE40-IO HOT 2
- No clear screen button on Olimex iCE40HX8K with ICE40-IO HOT 1
- Backspace on PS/2 keyboard sends '(' instead of '_' HOT 4
- DE0 board ignores colour settings. HOT 1
- Maybe error in Memory Map HOT 1
- Expanding RAM to 32KB HOT 3
- PS/2 and serial in ought to work at the same time
- No response on UART on ice40hx8k-evb HOT 1
- Possibility to apply for Zybo Zynq-7000
- How to Use USB Serial on Upduino V2.0 HOT 1
- top-level module name is undescriptive HOT 1
- Can this be used in Vivado? HOT 1
- Some debugging tehniques HOT 1
- Merging Lawrie's work HOT 4
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