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752-smartsimpoint

akankshac-073

Config files for my GitHub profile.

eemcs-wip

gem5

The official repository for the gem5 computer-system architecture simulator.

memory-subsystem-simulator

Memory Management Unit design consisting of a two-level hierarchical conventional TLB, L1 way-halting split cache, L2 cache, and main memory with pure paging as the memory management scheme, and page fault frequency as thrashing mechanism

mips-5-stage-pipelined-control-and-datapath

Implementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.

preemptive-test-scheduling-in-photonic-nocs

snipersim

The Sniper Multi-Core Simulator