Comments (3)
By the way, is there any way to explicit specify which register I want to use in an nsimd::pack?
I means I compile my project with
add_compile_options(-DAVX512_SKYLAKE -DFMA -march=skylake-avx512)
And I have two function. In function A, I want use 512-bits registers, but in function B, I want use 128-bits registers.
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Hi @luoming17
Horizontal sum
Indeed the addv
operator doe snot support integers yet. The reason is that there is two "ways" to do it:
- saturated horizontal sum
- standard C horizontal sum (with possible overflows/underflows)
Since then we have decided what to do but did not manage to find time to actually implement it:
- The
addv
operator will perform standard C horizontal sum. - A new
addvs
operator will perform saturated horizontal sum.
If you already have implementations, we would really appreciate to include them. You see the documentation on how to add a new operator if you wish.
Use 128-bits registers when compiling for AVX-512
You can of course use 128-bits registers when compiling for AVX/AVX2 or AVX-512:
#include <nsimd/nsimd-all.hpp>
void foo() {
// Native SIMD register:
// - __m128 when targeting SSE
// - __m256 when targeting AVX
// - __m512 when targeting AVX-512
nsimd::pack<float> a;
// __m128 whatever the target is
nsimd::pack<float, 1, nsimd::sse42> b;
}
Let me however warn you about this. This will make you code non portable. I do not know your use case but maybe what follows will apply to you:
#if defined(NSIMD_X86)
typedef nsimd::pack<float> pack_t;
typedef nsimd::pack<float, 1, nsimd::sse2> pack128_t;
#if defined(NSIMD_ARM)
#if NSIMD_WORD_SIZE == 32
typedef nsimd::pack<float> pack_t;
typedef nsimd::pack<float, 1, nsimd::neon128> pack128_t;
#else
typedef nsimd::pack<float> pack_t;
typedef nsimd::pack<float, 1, nsimd::aarch64> pack128_t;
#endif
#else
#error "Unsupported architecture"
#endif
This is not the first time we see this kind of demand. When we worked on GROMACS we add to write something like the above because GROMACS needs a 128-bits SIMD type. Maybe we should think of adding this into NSIMD. I have not though about this so I do not know if it is wise or not.
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Thank you, I have solved my problem.
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Related Issues (20)
- Performance different on X86 and ARM service HOT 2
- Vector<nsimd::pack<T>> HOT 4
- Support Reg Size /2 HOT 1
- NSIMD generates too much assembly HOT 5
- There is not ‘&’ bitwise operator for ’packl‘ type and no conversion of 'pack' and 'packl' type
- nsimd defines `i64` etc. in global namespace HOT 3
- Provide a C11 API for core
- NSIMD SVE intrinsics generates movprfx HOT 3
- Provide cbrt HOT 1
- Provide += operators etc.
- mask_for_loop_tail produces scalar code HOT 2
- Provide fabs, fmax, fmin HOT 2
- Use Sleef math functions to complete NSIMD
- Provide more "inline" operators such as copysign, isfinite, etc... HOT 2
- Implement a `flipsign` function HOT 1
- Provide a constexpr size function HOT 4
- Compile nsimd-2.2 on the ARM server HOT 2
- Document "andnot"
- Feature request: allow logical arguments for if_else1 HOT 2
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