- š Hi, Iām Aditya Remella
- š Iām interested in VLSI Design and Verification
- š± Iām currently learning Verilog HDL, SystemVerilog, UVM, FPGA, CMOS
- šļø Iām looking to collaborate on RTL Coding, Testbench and Testcase creation
- š« How to reach me https://www.linkedin.com/in/aditya-remella-188875198/
aditya892001 Goto Github PK
Name: Aditya Remella
Type: User
Location: Hyderabad