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Adil's Projects

aes-processor icon aes-processor

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

amba_apb_sram icon amba_apb_sram

AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM and can be used as standalone Verification IP (VIP).

cfu-playground icon cfu-playground

Want a faster ML processor? Do it yourself! -- A framework for playing with custom opcodes to accelerate TensorFlow Lite for Microcontrollers (TFLM).

r8051 icon r8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

riscv-vip icon riscv-vip

For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

systemc icon systemc

SystemC - design and testbench examples

systemverilog-1 icon systemverilog-1

This is a code repo for previous projects in Digital Design & Verification

tbengy icon tbengy

Python Tool for UVM Testbench Generation

uvmprimer icon uvmprimer

Contains the code examples from The UVM Primer Book sorted by chapters.

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