Comments (9)
The A64 and H5 may be similar enough that you could just use that. Otherwise we'll need to add something that narrows it down further like a longer string. I have the Pine64 if we need to go that route.
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Thanks for getting back to me, unfortunately the pin mapping is totally different, I have a local copy for the H5 based Orange Pi working fine, its just at I can see how to to have both the Pine A64 and the Orange Pi H5 at the same time, the problem being that both the A64 and H5 are identified as sun50iw1p1.
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Ok, it sounds like we'll have to narrow it down a bit further then. I just pulled out my Pine64. Let me see what I can find.
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Here's the results of cat /proc/cpuinfo
pi@pine64:~$ cat /proc/cpuinfo
processor : 0
Processor : AArch64 Processor rev 4 (aarch64)
Hardware : sun50iw1p1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 4
processor : 1
Processor : AArch64 Processor rev 4 (aarch64)
Hardware : sun50iw1p1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 4
processor : 2
Processor : AArch64 Processor rev 4 (aarch64)
Hardware : sun50iw1p1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 4
processor : 3
Processor : AArch64 Processor rev 4 (aarch64)
Hardware : sun50iw1p1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 4
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Here's the results of cat /proc/device-tree/compatible
pine64,pine64-plusallwinner,sun50i-a64
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I'm thinking possibly one CPU fields differs or possibly the sun50i-a64
inside of the device-tree/compatible results.
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cat/proc/cpuinfo
root@orangepizeroplus2-h5:/home/pi/pihome# cat /proc/cpuinfo
processor : 0
Processor : AArch64 Processor rev 4 (aarch64)
Hardware : sun50iw1p1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 4
processor : 1
Processor : AArch64 Processor rev 4 (aarch64)
Hardware : sun50iw1p1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 4
processor : 2
Processor : AArch64 Processor rev 4 (aarch64)
Hardware : sun50iw1p1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 4
processor : 3
Processor : AArch64 Processor rev 4 (aarch64)
Hardware : sun50iw1p1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 cpuid
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x0
CPU part : 0xd03
CPU revision : 4
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cat /proc/device-tree/compatible
xunlong,orangepi-zero-plus2allwinner,sun50i-h5
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Ok cool. I'm going to submit a PR that changes the A64 chip to use the dt-compatible value for detection and I would suggest you use that too.
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