Related Issues (20)
- Use an existing standard for start/stop/reset MMIO control registers
- [Fletchgen] Namespacing for the generated VHDL files
- Add codegen/test to CI
- Error in wheel build step of ci does not fail job
- Pin all dependencies HOT 3
- Update Cerata dependency
- [Fletchgen||C++] Builds with Clang fail since Arrow 0.17 upgrade HOT 2
- [|C++] when polling kernel completion, do not start with sleep
- Build Arrow from source when lib not found HOT 1
- Bump versions on develop branch to next release target
- Mismatch between bus address width and addresses passed through vhdmmio
- Release workflow trigger for assets is broken HOT 1
- Add warning output to Fletchgen for unused metadata fields
- pyfletchgen build is broken
- [Fletchgen|Python] Include VHDL support files in pyfletchgen
- Remove REG_WIDTH from AxiTop
- [Fletchgen] AXI top template sets BUS_BURST_MAX_LEN to BUS_ADDR_WIDTH
- Upgrade to Arrow 5.0
- Stringread example throws std::bad_alloc HOT 19
- Will you run fletcher on aliyun F3 platform ? HOT 1
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from fletcher.