Name: Abhraneel Saha
Type: User
Bio: pursuing BTech in Electrical and Electronics Engineering (expected 2025) at the Indian Institute of Technology Patna. Artificial Intelligence enthusiast.
Twitter: abhra_2609
Location: Bihta,Patna,Bihar
Abhraneel Saha's Projects
The hardware of a 16 bit x 16 bit multiplier is designed using Verilog HDL. The multiplication is performed using Vedic Mathematics which is proved to consume less power and faster than conventional multipliers. The sutra used here is "Urdhva-Tiryagbhyam sutra"
Prediction of the price of Airplane tickets(as per 2019 data) by using Machine Learning techniques(Random Forrest Regressor)
A simple bank management system using python-mysql.
A simple bank-management system using python-mysql
A simple application of AI-ML in Civil Engineering to predict the concrete compressive strength
Contains Data
This git repository contains all relevant datasets used and python notebooks for EY Techathon 4.0
Multi-UAV Placement and User Association in Uplink MIMO Ultra-Dense Wireless Networks
PD_data_exploration
Implementation of popular ML algorithms from scratch
A repo for learning ML and DS
Training a nanoGPT model to generate PG Wodehouse like text
Jupyter notebook with Pytorch implementation of Neural Ordinary Differential Equations
A quantum Safe Hardware security module for the automotive industry to authenticate SOTA
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NIST SP800-108 Feedback Mode based key generation scheme implemented on FPGA using Verilog
A Library for Advanced Deep Time Series Models.
A CNN model is used to predict traffic signals by feeding it images up-to a decent accuracy