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16bits-fast-fourier-transform-

This IP is to build a fast fourier transform 16bits with complex multiplier and complex adder

2-way-set-associative-cache-controller

Synthesizable and Parameterized Cache Controller in Verilog

32bit-mac-unit

32 bit Vedic Multiplier, using the Urdhava Triyagbhayam Sutra Criss Cross method, coded in Verilog

amba_axi_ahb_apb

AMBA bus lecture material

analog-virtualbox-vm-sky130a

Virtual Machine for analog with the open source Sky130A PDK

analog_matrix_multiplication

Build an analog module that perform multiplication on op-amps

apb-protocol

arm_amba_design

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

asic-labs-sp23

Lab specs for asic-labs-sp23 is organized here!

awesome-stars

Awesome List of my own!

axi-crossbar-sample-learning

An AXI4 crossbar implementation in SystemVerilog

axi4-interface

AXI4 and AXI4-Lite interface definitions

c2s2-serdes

cache

L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC

cache-controller

Two Level Cache Controller implementation in Verilog HDL

cache-design-verilog

design of a memory sub system with cache memory

caches

Verilog open-source cache implementations

cdc-example-no-vc_stat

A simple CDC example with gray counter and register

charles-designware-smic13

The design ware initialized by Charles, publishing standard Verilog modules and data path circuits for fast development of your own VLSI circuits

clock-tree-synthesis-studying

learning and gaining some insight into clock tree synsthesis

complex-number-multiplier

i built a 16bits signed complex number multiplier, the multiplier comprise of 32 adders 32bits signed that are use for multiplication and two adder for extending the sign of the multiplicant and multiplier.

cosim_bfm_library

HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI

cutie-not-relevent

[arXiv 2023] Putting the Object Back Into Video Object Segmentation

ddr-lpddr-wav

Wavious DDR (WDDR) Physical interface (PHY) Hardware

ddr-resources

DDR repository

ddr3-notes

My notes for DDR3 SDRAM controller

ddr5_phy

DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

deep_learning_blocks

DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep learning inference network.

deep_learning_curriculum

Language model alignment-focused deep learning curriculum

design-verification

Course content for the University of Bristol Design Verification course.