Name: Hans_Pham
Type: User
Company: HCM University of Technology
Bio: love tech and futurism
currently interested in TPU,CPU,GPU,NPU.
My youtube channel:
https://www.youtube.com/channel/UCZNl3FZHM5c8cAVC68Z0poA
Location: Ho Chi Minh city, Viet Nam
Blog: https://www.linkedin.com/in/kha%CC%89i-pha%CC%A3m-t%C3%A2%CC%81n-100540191/
Hans_Pham 's Projects
This IP is to build a fast fourier transform 16bits with complex multiplier and complex adder
Synthesizable and Parameterized Cache Controller in Verilog
32 bit Vedic Multiplier, using the Urdhava Triyagbhayam Sutra Criss Cross method, coded in Verilog
AMBA bus lecture material
Virtual Machine for analog with the open source Sky130A PDK
Build an analog module that perform multiplication on op-amps
Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
Lab specs for asic-labs-sp23 is organized here!
Awesome List of my own!
An AXI4 crossbar implementation in SystemVerilog
AXI4 and AXI4-Lite interface definitions
L1 Data, L1 Instruction and L2 Unified Cache Design FOR RV64IMC
Two Level Cache Controller implementation in Verilog HDL
design of a memory sub system with cache memory
Verilog open-source cache implementations
A simple CDC example with gray counter and register
The design ware initialized by Charles, publishing standard Verilog modules and data path circuits for fast development of your own VLSI circuits
learning and gaining some insight into clock tree synsthesis
i built a 16bits signed complex number multiplier, the multiplier comprise of 32 adders 32bits signed that are use for multiplication and two adder for extending the sign of the multiplicant and multiplier.
HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI
[arXiv 2023] Putting the Object Back Into Video Object Segmentation
Wavious DDR (WDDR) Physical interface (PHY) Hardware
DDR repository
My notes for DDR3 SDRAM controller
DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision
DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep learning inference network.
Language model alignment-focused deep learning curriculum
Course content for the University of Bristol Design Verification course.